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data sheet rev. 2.0, 2010-08-02 automotive power BTS5090-2EKA smart high-side power switch dual channel, 90m profet?+ 12v
data sheet 2 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3.1 pcb set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3.2 thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 turn on/off characteristics with resistive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 output clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.2 maximum load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 inverse current capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 electrical characteristics power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 loss of ground protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5 overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5.1 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.5.2 temperature limitation in the power dmos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5.3 short circuit appearance with channel in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.6 electrical characteristics fo r the protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 is pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 sense signal in different operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 sense signal in the nominal current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3.1 sense signal variation as a func tion of temperature and load current . . . . . . . . . . . . . . . . . . . 29 7.3.2 sense signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3.3 sense signal in open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.3.3.1 open load in on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.3.3.2 open load in off diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.3.3.3 open load diagnostic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.3.4 sense signal with out in short circuit to v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.3.5 sense signal in case of overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.3.6 sense signal in case of inverse current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4 electrical characteristics diagnostic function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.1 input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table of contents
data sheet 3 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA table of contents 8.2 den / dsel pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.3 input pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.1 minimum functional supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.2 undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.1.3 current consumption one channel active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.4 current consumption two channels active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1.5 standby current for whole device with load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.1 output voltage drop limitation at lo w load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.2 drain to source clamp volt age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2.3 slew rate at turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.4 slew rate at turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.5 turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.6 turn off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.7 turn on / off matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.8 switch on energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2.9 switch off energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.1 overload condition in the low voltage area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.2 overload condition in the high voltage area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4 diagnostic mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4.1 current sense at no load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4.2 open load detection threshold in on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4.3 sense signal maximum voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.4.4 sense signal maximum current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.5 input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5.1 input voltage threshold on to off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5.2 input voltage threshold off to on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.5.3 input voltage hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.5.4 input current high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.1 further application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
pg-dso-14-40 ep type package marking BTS5090-2EKA pg-dso-14-40 ep BTS5090-2EKA data sheet 4 rev. 2.0, 2010-08-02 profet?+ 12v smart high-side power switch BTS5090-2EKA 1overview application ? suitable for resistive, indu ctive and capacitive loads ? replaces electromechanical relays, fuses and discrete circuits ? most suitable for loads with high inrush current, such as lamps basic features ? two channel device ? very low stand-by current ? 3.3 v and 5 v compatible logic inputs ? electrostatic discha rge protection (esd) ? optimized electromagnetic compatibility ? logic ground independent from load ground ? very low power dmos leakage current in off state ? green product (rohs compliant) ? aec qualified description the BTS5090-2EKA is a 90 m dual channel smart high-side power switch, embedded in a pg-dso-14-40 ep, exposed pad package, providing protecti ve functions and diagnosis. the power transistor is built by an n-channel vertical power mosfet with charge pump. the device is int egrated in smart6 technology. it is specially designed to drive lamps up to 1 * p21w, as well as leds in the harsh automotive environment. table 1 product summary parameter symbol value operating voltage range v s(op) 5 v ... 28 v maximum supply voltage v s(ld) 41 v maximum on state resistance at t j = 150 c per channel r ds(on) 180 m nominal load current (one channel active) i l(nom)1 3.5 a nominal load current (both channels active) i l(nom)2 2.5 a typical current sense ratio k ilis 1500 minimum current limitation i l5(sc) 20 a maximum standby current with load at t j = 25 c i s(off) 500 na
data sheet 5 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA overview diagnostic functions ? proportional load current sense for both channels multiplexed ? open load in on and off ? short circuit to battery and ground ? overtemperature ? stable diagnostic signal during short circuit ? enhanced k ilis dependency with temperature and load current protection functions ? stable behavior during undervoltage ? reverse polarity protection with external components ? secure load turn-off during logic gr ound disconnect with external components ? overtemperature protection with restart ? overvoltage protection with external components ? voltage dependent current limitation ? enhanced short circuit operation
BTS5090-2EKA block diagram data sheet 6 rev. 2.0, 2010-08-02 profet?+ 12v 2 block diagram figure 1 block diagram for the BTS5090-2EKA block diagram dxs.vsd channel 0 v s out 0 in0 t driver logic gate control & charge pump load current sense and open load detection over temperature clamp for inductive load over current switch limit forward voltage drop detection voltage sensor gnd esd protection is den channel 1 dsel in1 control and protection circuit equivalent to channel 0 t v s out 1 internal power supply
data sheet 7 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA pin configuration 3 pin configuration 3.1 pin assignment figure 2 pin configuration 3.2 pin definitions and functions pin symbol function 1gnd ground; ground connection 2in0 input channel 0; input signal for ch annel 0 activation 3den diagnostic enable; digital signal to e nable/disable the diagnosis of the device 4is sense; sense current of the selected channel 5 dsel diagnostic selection; digital signal to select the channel to be diagnosed 6in1 input channel 1; input signal for ch annel 1 activation 7, 11 nc not connected; no internal connec tion to the chip 8, 9, 10 out1 output 1; protected high side power output channel 1 1) 1) all output pins of a given channel must be connected together on the pcb. all pi ns of an output are internally connected together. pcb traces have to be designed to withstand the maximum current which can flow. 12, 13, 14 out0 output 0; protected high side power output channel 0 1) cooling tab v s voltage supply; battery voltage pinout dual so14 .vsd out0 out0 out0 nc out1 out1 out1 gnd in0 den is dsel in1 nc 14 13 12 11 10 9 8 1 2 3 4 5 6 7
BTS5090-2EKA pin configuration data sheet 8 rev. 2.0, 2010-08-02 profet?+ 12v 3.3 voltage and current definition figure 3 shows all terms used in this data sheet, wit h associated convention for positive values. figure 3 voltage and current definition v s in0 in1 den dsel is gnd out0 out1 i in0 i in1 i den i dsel i is v s v in0 v in1 v den v dsel v is i s i gnd v ds0 v ds1 v out0 v out1 i out1 i out0 voltage and current convention.vsd
data sheet 9 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA general product characteristics 4 general product characteristics 4.1 absolute maximum ratings table 2 absolute maximum ratings 1) t j = -40c to +150c; (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. supply voltages supply voltage v s -0.3 ? 28 v ? p_4.1.1 reverse polarity voltage - v s(rev) 0?16v t < 2 min t a = 25 c r l 6 r gnd = 150 p_4.1.2 supply voltage for short circuit protection v bat(sc) 0?24 v 2) r ecu = 20 m r cable = 16 m /m l cable = 1 h/m, l = 0 or 5 m see chapter 6 and figure 53 p_4.1.3 supply voltage for load dump protection v s(ld) ? ? 41 v 3) r i = 2 r l = 6 p_4.1.12 short circuit capability permanent short circuit in pin toggles n rsc1 100 ? ? k cycle 2) 100 ppm t on = 300ms p_4.1.4 input pins voltage at input pins v in -0.3 ? ?6 7 v? t < 2 min p_4.1.13 current through input pins i in -2 ? 2 ma ? p_4.1.14 voltage at den pin v den -0.3 ? ?6 7 v? t < 2 min p_4.1.15 current through den pin i den -2 ? 2 ma ? p_4.1.16 voltage at dsel pin v dsel -0.3 ? ?6 7 v? t < 2 min p_4.1.17 current through dsel pin i dsel -2 ? 2 ma ? p_4.1.18 sense pin voltage at is pin v is -0.3 ? v s v ? p_4.1.19 current through is pin i is -25 ? 50 ma ? p_4.1.20 power stage load current | i l |?? i l(lim) a ? p_4.1.21 power dissipation (dc) p tot ??1.9w t a = 85 c t j < 150 c p_4.1.22
BTS5090-2EKA general product characteristics data sheet 10 rev. 2.0, 2010-08-02 profet?+ 12v notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. maximum energy dissipation single pulse (one channel) e as ??42mj i l(0) = 3 a t j(0) = 150 c v s = 13.5 v p_4.1.23 voltage at power transistor v ds ? ? 41 v ? p_4.1.26 currents current through ground pin i gnd -10 -150 ?10 20 ma ? t < 2 min p_4.1.27 temperatures junction temperature t j -40 ? 150 c ? p_4.1.28 storage temperature t stg -55 ? 150 c ? p_4.1.30 esd susceptibility esd susceptibility (all pins) v esd -2 ? 2 kv 4) hbm p_4.1.31 esd susceptibility out pin vs. gnd and v s connected v esd -4 ? 4 kv 4) hbm p_4.1.32 esd susceptibility v esd -500 ? 500 v 5) cdm p_4.1.33 esd susceptibility pin (corner pins) v esd -750 ? 750 v 5) cdm p_4.1.34 1) not subject to production test. specified by design. 2) hardware set-up in accordance to aec q100-012 and aec q101-006. 3) v s(ld) is setup without the dut connect ed to the generator per iso 7637-1. 4) esd susceptibility hbm according to eia/jesd 22-a 114b. 5) ?cdm? eia/jesd22-c101 or esda stm5.3.1 table 2 absolute maximum ratings (cont?d) 1) t j = -40c to +150c; (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max.
data sheet 11 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA general product characteristics 4.2 functional range table 3 functional range t j = -40c to +150c ; (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. nominal operating voltage v nom 8 13.5 18 v ? p_4.2.1 extended operating voltage v s(op) 5?28 v 2) v in = 4.5 v r l = 6 v ds < 0.5 v see figure 15 p_4.2.2 minimum functional supply voltage v s(op)_min 3.8 4.3 5 v 1) v in = 4.5 v r l = 6 from i out = 0 a to v ds < 0.5 v; see figure 15 see figure 29 p_4.2.3 undervoltage shutdown v s(uv) 3 3.5 4.1 v 1) v in = 4.5 v v den = 0 v r l = 6 from v ds < 1 v; to i out = 0 a see figure 15 see figure 30 p_4.2.4 undervoltage shutdown hysteresis v s(uv)_hys ? 850 ? mv 2) ? p_4.2.13 operating current one channel active i gnd_1 ?3.56ma v in = 5.5 v v den = 5.5 v device in r ds(on) v s = 18 v see figure 31 p_4.2.5 operating current all channels active i gnd_2 ?58ma v in = 5.5 v v den = 5.5 v device in r ds(on) v s = 18 v see figure 32 p_4.2.6 standby current for whole device with load (ambiente) i s(off) ?0.10.5 a 1) v s = 18 v v out = 0 v v in floating v den floating t j 85 c see figure 33 p_4.2.7
BTS5090-2EKA general product characteristics data sheet 12 rev. 2.0, 2010-08-02 profet?+ 12v note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance 4.3.1 pcb set up figure 4 2s2p pcb cross section maximum standby current for whole device with load i s(off)_150 ?320 a v s = 18 v v out = 0 v v in floating v den floating t j = 150 c see figure 33 p_4.2.10 standby current for whole device with load, diagnostic active i s(off_den) ?0.6?ma 2) v s = 18 v v out = 0 v v in floating v den = 5.5 v p_4.2.8 1) test at t j = -40c only 2) not subject to production test. specified by design. table 4 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to soldering point r thjs ?5?k/w 1) 1) not subject to production test. specified by design. p_4.3.1 junction to ambient both channels active r thja ?34?k/w 1) 2) 2)specified r thja value is accordin g to jedec jesd51-2,-5,-7 at natura l convection on fr4 2s2p board; the product (chip + package) was simulated on a 76.4 x 11 4.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable, a thermal via array under the exposed pad contacts the first inner copper layer. please refer to figure 4 and figure 5 . p_4.3.2 table 3 functional range (cont?d) t j = -40c to +150c ; (unless otherwise specified) parameter symbol values unit note / test condition number min. typ. max. 1.5mm 70m 35m 0.3mm pcb 2s2p.vsd
data sheet 13 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA general product characteristics figure 5 pc board top and bottom view for the rmal simulation with 600 mm2 cooling area 4.3.2 thermal impedance figure 6 typical thermal impedance. pcb set up according figure 5 thermique so14.vsd 1 2 3 4 5 6 7 14 13 12 11 10 9 8 cooling tab v s pcb top view pcb bottom view 0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000 time [sec] zth-ja [k/w ] 2s2p 1s0p - 600 mm2 1s0p - 300 mm2 1s0p - footprint
BTS5090-2EKA general product characteristics data sheet 14 rev. 2.0, 2010-08-02 profet?+ 12v figure 7 typical thermal resistance. pcb set up 1s0p 0 100 200 300 400 500 600 700 30 40 50 60 70 80 90 100 rthja [k/w] area [mm 2 ] footprint 1s0p
data sheet 15 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA power stage 5 power stage the power stages are built using an n-channel vertical power mosfet (dmos) with charge pump. 5.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage as well as the junction temperature t j . figure 8 shows the dependencies in terms of temperature and supp ly voltage for the typical on-state resistance. the behavior in reverse polarity is described in chapter 6.4 . figure 8 typical on-state resistance a high signal at the input pin (see chapter 8 ) causes the power dmos to switch on with a dedicated slope, which is optimized in terms of emc emission. 5.2 turn on/off characteris tics with resistive load figure 9 shows the typical timing when switching a resistive load. figure 9 switching a r esistive load timing rdson_90.vsd 50 60 70 80 90 100 110 120 130 140 150 160 -40 -10 20 50 80 110 140 junction temperature (tj) r ds(on) (m ) 0 50 100 150 200 0 3 6 9 12 15 18 supply voltage v s (v) r ds(on) (m ) in t v out t on t on_delay t off 90% v s 10% v s v in_h v in_l t switching times.vsd t off_delay 30% v s 70% v s dv/dt on dv/dt off
BTS5090-2EKA power stage data sheet 16 rev. 2.0, 2010-08-02 profet?+ 12v 5.3 inductive load 5.3.1 output clamping when switching off inductive loads wit h high side switches, the voltage v out drops below ground potential, because the inductance intends to continue driving the current. to prevent the destr uction of the device by avalanche due to high voltages, there is a voltage clamp mechanism z ds(az) implemented that limits negative output voltage to a certain level ( v s - v ds(az) ). please refer to figure 10 and figure 11 for details. nevertheless, the maximum allowed load inductance is limited. figure 10 output clamp (out0 and out1) figure 11 switching an inductive load timing v bat v out i l l, r l v s out v ds logic in v in output clamp.svg z ds(az) gnd z gnd in v out i l v s v s -v ds(az) t t t switching an inductance.vsd
data sheet 17 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA power stage 5.3.2 maximum load inductance during demagnetization of inductive lo ads, energy has to be dissipated in the BTS5090-2EKA. this energy can be calculated with following equation: (1) following equation simplifies under the assumption of r l = 0 . (2) the energy, which is converted in to heat, is limited by the thermal design of the component. see figure 12 for the maximum allowed energy dissipation as a function of the load current. figure 12 maximum energy dissipation si ngle pulse, t j(0) = 150 c; v s = 13.5v 5.4 inverse current capability in case of inverse current, meaning a voltage v inv at the output higher than the supply voltage v s , a current i inv will flow from output to v s pin via the body diode of the power transistor (please refer to figure 13 ). the output stage follows the state of the in pin, except if the in pi n goes from off to on during inverse. in that particular case, the output stage is kept off until the inverse current disappears. nevertheless, the current i inv should not be higher than i l(inv) . otherwise, the second channel can be corrup ted and erratic behavior can be observed. if the affected channel is off, the diagnostic will detect an open load at off. if the affected channel is on, the diagnostic will detect open load at on (the overtemp erature signal is inhibited) . at the appearance of v inv , a parasitic diagnostic can be observed at the unaffected chann el. after, the diagnosis is valid and reflects the output state. at v inv vanishing, the diagnosis is valid and reflects the output state. during inverse current, no protection function are available. ev ds az () l r l ------ v s v ds az () ? r l -------------------------------- 1 r l i l v s v ds az () ? -------------------------------- ? ?? ?? ln i l + = e 1 2 -- - li 2 1 v s v s v ds az () ? -------------------------------- ? ?? ?? = 1 10 100 1000 0123456 i l [a] e as [mj] eas90.vsd
BTS5090-2EKA power stage data sheet 18 rev. 2.0, 2010-08-02 profet?+ 12v figure 13 inverse current circuitry out v s v bat i l(inv) ol comp. inverse current.svg v inv inv comp. gate driver device logic gnd z gnd
data sheet 19 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA power stage 5.5 electrical charact eristics power stage table 5 electrical characteristics: power stage v s = 8 v to 18 v, t j = -40c to +150c (unless otherwise specified). typical values are given at v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. on-state resistance per channel r ds(on)_150 67 170 180 m i l = i l4 = 4 a v in = 4.5 v t j = 150 c see figure 8 p_5.5.1 on-state resistance per channel r ds(on)_25 ?90?m 1) t j = 25 c p_5.5.21 nominal load current one channel active i l(nom)1 ?3.5?a 1) t a = 85 c t j < 150 c p_5.5.2 nominal load current all channel active i l(nom)2 ?2.5?a p_5.5.3 output voltage drop limitation at small load currents v ds(nl) ?1025mv i l = i l0 = ma see figure 34 p_5.5.4 drain to source clamping voltage v ds(az) = [ v s - v out ] v ds(az) 41 47 53 v i ds = 20 ma see figure 11 see figure 35 p_5.5.5 output leakage current per channel; t j 85 c i l(off) ?0.10.5 a 2) v in floating v out = 0 v t j 85 c p_5.5.6 output leakage current per channel; t j = 150 c i l(off)_150 ?1,510 a v in floating v out = 0 v t j = 150 c p_5.5.8 inverse current capability i l(inv) ?2.5?a 1) v s < v outx p_5.5.9 slew rate 30% to 70% v s d v /d t on 0.1 0.25 0.5 v/ s r l = 6 v s = 13.5 v see figure 9 see figure 36 see figure 37 see figure 38 see figure 39 see figure 40 p_5.5.11 slew rate 70% to 30% v s -d v /d t off 0.1 0.25 0.5 v/ s p_5.5.12 slew rate matching d v /d t on - d v /d t off d v /d t -0.15 0 0.15 v/ s p_5.5.13 turn-on time to v out = 90% v s t on 30 100 230 s p_5.5.14 turn-off time to v out = 10% v s t off 30 100 230 s p_5.5.15 turn-on / off matching t off - t on t sw -50 0 50 s p_5.5.16 turn-on time to v out = 10% v s t on_delay 10 35 100 s p_5.5.17 turn-off time to v out = 90% v s t off_delay 10 35 100 s p_5.5.18
BTS5090-2EKA power stage data sheet 20 rev. 2.0, 2010-08-02 profet?+ 12v switch on energy e on ?0.8?mj 1) r l = 6 v out = 90% v s v s = 18 v see figure 41 p_5.5.19 switch off energy e off ?0.7?mj 1) r l = 6 v out = 10% v s v s = 18 v see figure 42 p_5.5.20 1) not subject to production test, specified by design. 2) test at t j = -40c only table 5 electrical characteristics: power stage (cont?d) v s = 8 v to 18 v, t j = -40c to +150c (unless otherwise specified). typical values are given at v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
data sheet 21 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA protection functions 6 protection functions the device provides integrated protecti on functions. these functions are designed to prevent the destruction of the ic from fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are designe d for neither continuous nor repetitive operation. 6.1 loss of ground protection in case of loss of the module ground and the load re mains connected to ground, th e device protects itself by automatically turning off (when it was previously on) or remains off, regardless of the voltage applied on in pins. in case of loss of device ground, it?s recommended to use input resistors between the microcontroller and the BTS5090-2EKA to ensure sw itching off of channels. in case of loss of module or device ground, a current ( i out(gnd) ) can flow out of the dmos. figure 14 sketches the situation. z gnd can be either resistor or diode. figure 14 loss of ground protection with external components 6.2 undervoltage protection between v s(uv) and v s(op) , the undervoltage mechanism is triggered. v s(op) represents the minimum voltage where the switching on an d off can takes place. v s(uv) represents the minimum voltage the switch can hold on. if the supply voltage is below the undervoltage mechanism v s(uv) , the device is off (turns off). as soon as the supply voltage is above the undervoltage mechanism v s(op) , then the device can be s witched on. when the switch is on, protection functions are operational. nevertheless, the di agnosis is not guaranteed until v s is in the v nom range. figure 15 sketches the undervoltage mechanism. inx den is zd esd gnd outx v s v bat z d(az) logic dsel loss of ground protection.svg i out(gnd) z ds(az) r in r den r dsel r sense r is z is(az) z gnd
BTS5090-2EKA protection functions data sheet 22 rev. 2.0, 2010-08-02 profet?+ 12v figure 15 undervoltage behavior 6.3 overvoltage protection there is an integrated clamp mechan ism for overvoltage protection (z d(az) ). to guarantee this mechanism operates properly in the application, the current in the zener diode has to be limited by a ground resistor. figure 16 shows a typical application to withstand overvoltage issues. in case of supply voltage higher than v s(az) , the power transistor switches on and the voltage across the logic section is clamped. as a result, the internal ground potential rises to v s - v s(az) . due to the esd zener diodes, the potential at pin inx, dsel and den rises almost to that potential, depending on the impedance of the conne cted circuitry. in the case the device was on, prior to overvoltage, the bts509 0-2eka remains on. in the case the bts509 0-2eka was off, prior to overvoltage, the power transistor can be activated. in the case the supply voltage is in above v bat(sc) and below v ds(az) , the output transistor is still operational and follows the input. if at least one channel is in the on state, parameters are no longer guaranteed and lifetime is reduced compared to the nominal supply voltage range. this especially impacts the short circuit robustness, as well as the maximum energy e as capability. z gnd as a resistor (150 ) will offer superior results compared to a diode and resistor (1 k ). figure 16 overvoltage protecti on with external components undervoltage behavior .vsd v out v s(op) v s(uv) v s inx den is zd esd gnd outx v s v bat z d(az) logic dsel overvoltage protection.svg z ds(az) in0 in1 r in r den r dsel r sense r is i sov z is(az) z gnd
data sheet 23 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA protection functions 6.4 reverse polarity protection in case of reverse polarity, the intrinsic body diodes of the power dmos causes power dissipation. the current in this intrinsic body diode is limited by the load itself. addi tionally, the current into the ground path and the logic pins has to be limited to the maximum current described in chapter 4.1 with an external resistor. figure 17 shows a typical application. r gnd resistor is used to limit the current in the zener protec tion of the device. resistors r dsel , r den , and r in are used to limit the current in the logic of the device and in the esd protection stage. r sense is used to limit the current in the sense transistor wh ich behaves as a diode. the recommended value for r den = r dsel = r in = r sense = 4.7 k . z gnd can be either a 150 resistor or schottky diode with 1 k resistor in parallel. in case the overvoltage is not considered in the application, r gnd can be replaced by a schottky diode and 1k resistor in parallel. optionally a capacitor in parallel is recomm ended for emc reasons. during reverse polarity, no protection functions are available. figure 17 reverse polarity protection with external components 6.5 overload protection in case of overload, such as high inrush of cold lamp f ilament, or short circuit to ground, the BTS5090-2EKA offers several protection mechanisms. 6.5.1 current limitation at first step, the instantaneous power in the switch is maintained at a safe value by limiting the current to the maximum current allowed in the switch i l(sc) . during this time, the dmos temper ature is increasing, which affects the current flowing in the dmos. the current limitation value is v ds dependent. figure 18 shows the behavior of the current limitation as a function of the drain to source voltage. inx den is zd esd gnd outx v s -v s(rev) z d(az) logic dsel reverse polarity.vsd z ds(az) in0 r in r den r dsel r sense r is v ds(rev) micro controller protection diodes z is(az) z gnd
BTS5090-2EKA protection functions data sheet 24 rev. 2.0, 2010-08-02 profet?+ 12v figure 18 current limitation (typical behavior) 6.5.2 temperature limita tion in the power dmos each channel incorporates both an absolute ( t j(sc) ) and a dynamic ( t j(sw) ) temperature sensor. activation of either sensor will cause an overheated channel to switch off to prevent destruction. any protective switch off latches the output until the temperature has reached an acceptable value. figure 19 gives a sketch of the situation. the t step describes the device?s warming, due to the overcurrent in the channel. a retry strategy is implemented such that when the dm os temperature has cooled down enough, the switch is switched on again, if the in pin si gnal is still high (restart behavior).
data sheet 25 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA protection functions figure 19 overload protection note: for better understanding, the time scale is not linear. the real timing of this drawing is application dependant and cannot be described. 6.5.3 short circuit appearan ce with channel in parallel the two channels are not synchronized in the restart even t. when the two channels are in temperature limitation, the channel which has cooled down the fastest doesn?t wait the second one to be cooled down as well to restart. thus, it is not recommended to use the device with channel in parallel. in t i l t i l(x)sc i is t 0a i is(fault) v den t 0v t dmos t t step t a t j(s w) t j(s w ) t j(s w) hard start.vsd t sis( fault) i l(nom) i l(nom) / k ilis t sis (ot _bl ank) t j( s c) t sis (off ) load current limitation phase load current below limitation phase
BTS5090-2EKA protection functions data sheet 26 rev. 2.0, 2010-08-02 profet?+ 12v 6.6 electrical characteristi cs for the protection functions table 6 electrical characteristics: protection v s = 8 v to 18 v, t j = -40c to +150c (unless otherwise specified). typical values are given at v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. loss of ground output leakage current while gnd disconnected i out(gnd) ?0.1?ma 1) 2) v s = 28 v see figure 14 1) all pins are disconnected except v s and out. 2) not subject to production test, specified by design p_6.6.1 reverse polarity drain source diode voltage during reverse polarity v ds(rev) 200 650 700 mv i l = - 2 a t j = 150 c see figure 17 p_6.6.2 overvoltage overvoltage protection v s(az) 41 47 53 v i sov = 5 ma see figure 16 p_6.6.3 overload condition load current limitation i l5(sc) 20 30 40 a 3) v ds = 5 v see figure 18 and figure 43 3) test at t j = -40c only p_6.6.4 load current limitation i l28(sc) ?15?a 2) v ds = 28 v see figure 18 and figure 44 p_6.6.7 short circuit current during over temperature toggling i l(rms) ?3?a 2) v in = 4.5 v r short = 100 m l short = 5 h p_6.6.12 dynamic temperature increase while switching t j(sw) ?80?k 4) see figure 19 4) functional test only p_6.6.8 thermal shutdown temperature t j(sc) 150 170 4) 200 4) c 5) see figure 19 5) test at t j = +150c only p_6.6.10 thermal shutdown hysteresis t j(sc) ? 20 ? k 5) 4) see figure 19 p_6.6.11
data sheet 27 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA diagnostic functions 7 diagnostic functions for diagnosis purpose, the BTS5090-2EKA provides a comb ination of digital and anal og signals at pin is. these signals are called sense. in case the diagnostic is dis abled via den, pin is becomes high impedance. in case den is activated, the sense of the channel x is enabled/disabled via associated pin dsel. table 7 gives the truth table. 7.1 is pin the BTS5090-2EKA provides a sense current written i is at pin is. as long as no ?hard? failure mode occurs (short circuit to gnd / current limitation / ov ertemperature / excessive dynamic tem perature increase or open load at off) a proportional signal to the load current (ratio k ilis = i l / i is ) is provided. the complete is pin and diagnostic mechanism is described on figure 20 . the accuracy of the sense depends on temperature and load current. the is pin multiplexes the current i is(0) and i is(1) , via the pin dsel. thanks to this multiplexing, the matching between k ilischannel0 and k ilischannel1 is optimized. due to the esd protection, in connection to v s , it is not recommended to share the is pin with other devices if these devices are using another battery feed. the consequence is that the unsupplied device woul d be fed via the is pin of the supplied device. figure 20 diagnostic block diagram table 7 diagnostic truth table den dsel is 0 don?t care z 1 0 sense output 0 i is(0) 1 1 sense output 1 i is(1) v s i is0 = i l0 / k ilis den is 0 1 dsel sense schematic.svg i is1 = i l1 / k ilis 1 0 z is(az) i is(fault) fault
BTS5090-2EKA diagnostic functions data sheet 28 rev. 2.0, 2010-08-02 profet?+ 12v 7.2 sense signal in different operating modes table 8 gives a quick reference for the state of the is pin during device operation. table 8 sense signal, function of operation mode operation mode input level channel x den 1) 1) the table doesn?t indicate but it is assumed that the appropriate channel is selected via the dsel pin. output level diagnostic output normal operation off h z z short circuit to gnd ~ gnd z overtemperature z z short circuit to v s v s i is(fault) open load < v ol(off) > v ol(off) 2) 2) with additional pull-up resistor. z i is(fault) inverse current ~ v inv i is(fault) normal operation on ~ v s i is = i l / k ilis current limitation < v s i is(fault) short circuit to gnd ~ gnd i is(fault) overtemperature t j(sw) event z i is(fault) short circuit to v s v s i is < i l / k ilis open load ~ v s 3) 3) the output current has to be smaller than i l(ol) . i is < i is(ol) inverse current ~ v inv i is < i is(ol) 4) 4) after maximum t inv . underload ~ v s 5) 5) the output current has to be higher than i l(ol) . i is(ol) < i is < i l(nom) / k ilis don?t care don?t care l don?t care z
data sheet 29 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA diagnostic functions 7.3 sense signal in th e nominal current range figure 21 and figure 22 show the current sense as a function of the load current in the power dmos. usually, a pull-down resistor r is is connected to the is pin. this resistor has to be higher than 560 to limit the power losses in the sense circuitry. a typical value is 1.2 k . the blue curve represents the ideal sense, assuming an ideal k ilis factor value. the red curves show the accuracy the device provides across full temperature range, at a defined current. figure 21 current sense for nominal load 7.3.1 sense signal variat ion as a function of temp erature and load current in some applications a better accuracy is required around half the nominal current i l(nom) . to achieve this accuracy requirement, a calibration on the application is possible. to avoid multiple calibration points at different load and temperature conditions, the BTS5090-2EKA allows limited derating of the k ilis value, at nominal load current ( i l3 ; t j = +25 c). this derating is described by the parameter k ilis . figure 22 shows the behavior of the sense current, assuming one calibration point at nominal load at +25 c. the blue line indicates the ideal k ilis ratio. the green lines indicate the derating on the parameter across temperature and voltage, assuming one calibration point at nominal temperature and nominal battery voltage. the red lines indicate the k ilis accuracy without calibration. 0.0 1.0 2.0 3.0 4.0 5.0 6.0 01234567 i l [a] i is [m a] k ilis ideal i is = kilis bts5090 k ilis4 k ilis3 k ilis2 k ilis1 i l
BTS5090-2EKA diagnostic functions data sheet 30 rev. 2.0, 2010-08-02 profet?+ 12v figure 22 improved sense accuracy with one calibration point 7.3.2 sense signal timing figure 23 shows the timing during settling and disabling of the sense. figure 23 sense settling / disabling timing v inx t i l t i is t v den t t sis(on) t sis(off) t onx 90% of i is static 90% of i l static t sis(on_den) t sis(lc) v iny t i ly t v dsel t t sis(chc) current sense settling disabling time .vsd t onx t offx t ony
data sheet 31 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA diagnostic functions 7.3.3 sense signal in open load 7.3.3.1 open load in on diagnostic if the channel is on, a leakage curr ent can still flow through an open load, for exampl e due to humidity. the parameter i l(ol) gives the threshold of recognition fo r this leakage current. if the current i l flowing out the power dmos is below this value, the device recognizes a failure , if the den (and dsel) is selected. in that case, the sense current is below i is(ol) . otherwise, the minimum sense cu rrent is given above parameter i is(ol) . figure 24 shows the sense current behavior in this area. the red curve shows a typical product curve. the blue curve shows the ideal k ilis ratio. figure 24 current sense ratio for low currents 7.3.3.2 open load in off diagnostic for open load diagnosis in off-state, an external output pull-up resistor ( r ol ) is recommended. for the calculation of pull-up resistor value, the leak age currents and the open load threshold voltage v ol(off) have to be taken into account. figure 25 gives a sketch of the situation. i leakage defines the leakage current in the complete system, including i l(off) (see chapter 5.5 ) and external leakages, e.g, due to humidity, corrosion, etc.... in the application. to reduce the stand-by current of the system, an open load resistor switch s ol is recommended. if the channel x is off, the output is no longer pulled down by the load and v out voltage rises to nearly v s . this is recognized by the device as an open load. the voltage threshold is given by v ol(off) . in that case, the sen se signal is switched to the i is(fault) . an additional r pd resistor can be used to pull v out to 0v. otherwise, the out pin is floating. this resistor can be used as well for short circuit to battery detection, see chapter 7.3.4 . i is i l sense for ol .vsd i l(ol) i is(ol)
BTS5090-2EKA diagnostic functions data sheet 32 rev. 2.0, 2010-08-02 profet?+ 12v figure 25 open load detection in off electrical equivalent circuit 7.3.3.3 open load diagnostic timing figure 26 shows the timing during either open load in on or off condition when the den pin is high. please note that a delay t sis(fault_ol_off) has to be respecte d after the falling edge of th e input, when applying an open load in off diagnosis request, otherwise the diagnosis can be wrong. figure 26 sense signal in open load timing out v s s ol v bat v ol(off) i leakage i is(fault) is i loff ol comp. open load in off.svg r ol z gnd r is r leakage gnd r pd v in t v out t i is t t sis(lc) 90% of i iis(fault) static t sis(fault_ol_off) error settling disabling time.vsd v s -v ol(off) r ds(on) x i l i out load is present open load shutdown with load t
data sheet 33 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA diagnostic functions 7.3.4 sense signal with out in short circuit to v s in case of a short circuit between the output-pin and the v s pin, all or portion (depending on the short circuit impedance) of the load current will flow thro ugh the short circuit. as a resul t, a lower current compared to the normal operation will flow th rough the dmos of the BTS5090-2EKA, which can be recognized at the sense signal. the open load at off detection circuitry ca n also be used to distinguish a short circuit to v s . in that case, an external resistor to ground r sc_vs is required. figure 27 gives a sketch of the situation. figure 27 short circuit to battery detecti on in off electrical equivalent circuit 7.3.5 sense signal in case of overload an overload condition is defined by a current flowing out of the dmos reaching the current limitation and / or the absolute dynamic temperature swing t j(sw) is reached, and / or the juncti on temperature reaches the thermal shutdown temperature t j(sc) . please refer to chapter 6.5 for details. in that case, the sense signal given is by i is(fault) when the diagnostic is selected. the device has a thermal restart behavior, such th at when the overtemperature or the exceed dynamic temperature condition has disappeared, t he dmos is reactivated if the in is still at logical leve l one. if the den pin is activated, and dsel pin is selected to the corr ect channel, sense is not toggling with the restart mechanism and remains to i is(fault) . 7.3.6 sense signal in case of inverse current in the case of in verse current, the sense signal of the affected channel will indicate open load in off state and indicate open load in on state. the unaffected channel indicates normal behavior as long as the i inv current is not exceeding the maximum value specified in chapter 5.4 . v s v bat v ol(off) i is(fault) is ol comp. short circuit to vs.svg v bat out gnd z gnd r sc_vs r is
BTS5090-2EKA diagnostic functions data sheet 34 rev. 2.0, 2010-08-02 profet?+ 12v 7.4 electrical character istics diagnostic function table 9 electrical characteristics: diagnostics v s = 8 v to 18 v, t j = -40c to +150c (unless otherwise specified). typical values are given at v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. load condition threshold for diagnostic open load detection threshold in off state v s - v ol(off) 4?6v 1) v in = 0 v v den = 4.5 v see figure 26 p_7.5.1 open load detection threshold in on state i l(ol) 5?30 ma v in = v den = 4.5 v i is(ol) = 8 a see figure 24 see figure 46 p_7.5.2 sense pin is pin leakage current when sense is disabled i is_(dis) ??1 a 1) v in = 4.5 v v den = 0 v i l = i l4 = 4 a p_7.5.4 sense signal saturation voltage v s - v is (range) 0?3v 3) v in = 0 v v out = v s > 10 v v den = 4.5 v i is = 6 ma see figure 47 p_7.5.6 sense signal maximum current in fault condition i is(fault) 61535 ma v is = v in = v dsel = 0 v v out = v s > 10 v v den = 4.5 v see figure 20 see figure 48 p_7.5.7 sense pin maximum voltage v is(az) 41 47 53 v i is = 5 ma see figure 20 p_7.5.3 current sense ratio signal in the nominal area, stable load current condition current sense ratio i l0 = 50 ma k ilis0 -50 1650 +50 % v in = 4.5 v v den = 4.5 v see figure 21 t j = -40 c; 150 c p_7.5.8 current sense ratio i l1 = 0.5 a k ilis1 -34 1500 +34 % p_7.5.9 current sense ratio i l2 = 1 a k ilis2 -13 1500 +13 % p_7.5.10 current sense ratio i l3 = 2 a k ilis3 -9 1500 +9 % p_7.5.11 current sense ratio i l4 = 4 a k ilis4 -8 1500 +8 % p_7.5.12 k ilis derating with current and temperature k ilis -8 0 +8 % 3) k ilis3 versus k ilis2 see figure 22 p_7.5.17 diagnostic timing in normal condition
data sheet 35 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA diagnostic functions current sense settling time to k ilis function stable after positive input slope on both input and den t sis(on) 0?250 s 3) v den = v in = 0 to 4.5 v v s = 13.5 v r is = 1.2 k c sense < 100 pf i l = i l3 = 2 a see figure 23 p_7.5.18 current sense settling time with load current stable and transition of the den t sis(on_den) 0?20 s 1) v in = 4.5 v v den = 0 to 4.5 v r is = 1.2 k c sense < 100 pf i l = i l3 = 2 a see figure 23 p_7.5.19 current sense settling time to i is stable after positive input slope on current load t sis(lc) 0?20 s 1) v in = 4.5 v v den = 4.5 v r is = 1.2 k c sense < 100 pf i l = i l2 = 1 a to i l = i l3 = 2 a see figure 23 p_7.5.20 diagnostic timing in open load condition current sense settling time to i is stable for open load detection in off state t sis(fault_ol_ off) 0?150 s 1) v in = 0v v den = 0 to 4.5 v r is = 1.2 k c sense < 100 pf v out = v s = 13.5 v see figure 26 p_7.5.22 diagnostic timing in overload condition current sense settling time to i is stable for overload detection t sis(fault) 0?250 s 1) 2) v in = v den = 0 to 4.5 v r is = 1.2 k c sense < 100 pf v ds = 5 v see figure 19 p_7.5.24 current sense over temperature blanking time t sis(ot_blank) ? 350 ? s 3) v in = v den = 4.5 v r is = 1.2 k c sense < 100 pf v ds = 5 v to 0 v see figure 19 p_7.5.32 table 9 electrical characteristics: diagnostics (cont?d) v s = 8 v to 18 v, t j = -40c to +150c (unless otherwise specified). typical values are given at v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
BTS5090-2EKA diagnostic functions data sheet 36 rev. 2.0, 2010-08-02 profet?+ 12v diagnostic disable time den transition to i is < 50% i l /k ilis t sis(off) 0?30 s 1) v in = 4.5 v v den = 4.5 v to 0 v r is = 1.2 k c sense < 100 pf i l = i l3 = 2 a see figure 23 p_7.5.25 current sense settling time from one channel to another t sis(chc) 0?20 s v in0 = v in1 = 4.5 v v den = 4.5 v v dsel = 0 to 4.5 v r is = 1.2 k c sense < 100 pf i l(out0) = i l3 = 2 a i l(out1) = i l2 = 1 a see figure 23 p_7.5.26 1) dsel pin select channel 0 only. 2) test at t j = -40c only 3) not subject to production test, specified by design table 9 electrical characteristics: diagnostics (cont?d) v s = 8 v to 18 v, t j = -40c to +150c (unless otherwise specified). typical values are given at v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max.
data sheet 37 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA input pins 8 input pins 8.1 input circuitry the input circuitry is compatible with 3.3 and 5 v microcontr ollers. the concept of the input pin is to react to voltage thresholds. an implemented schmidt trigger avoids any unde fined state if the voltage on the input pin is slowly increasing or decreasing. the output is either off or on but cannot be in a linear or undefined state. the input circuitry is compatible with pwm applications. figure 28 shows the electrical equivalent input circuitry. in case the pin is not needed, it must be left opened, or must be connected to device ground (and not module ground) via a 4.7k input resistor. figure 28 input pin circuitry 8.2 den / dsel pin the den / dsel pins enable and disable the diagnostic functionality of the device. the pins have the same structure as the input pins, please refer to figure 28 . 8.3 input pin voltage the in, dsel and den use a comparator with hysteresis. t he switching on / off takes place in a defined region, set by the thresholds v in(l) max. and v in(h) min. the exact value where the on and off take place are unknown and depends on the process, as well as the temperature. to avoid cross talk and parasitic turn on and off, a hysteresis is implemented. this ensures a certain immunity to noise. gnd in input circuitry.vsd
BTS5090-2EKA input pins data sheet 38 rev. 2.0, 2010-08-02 profet?+ 12v 8.4 electrical characteristics table 10 electrical characteristics: input pins v s = 8 v to 18 v, t j = -40c to +150c (unless otherwise specified). typical values are given at v s = 13.5 v, t j = 25 c parameter symbol values unit note / test condition number min. typ. max. input pins characteristics low level input voltage range v in(l) -0.3 ? 0.8 v see figure 49 p_8.4.1 high level input voltage range v in(h) 2 ? 6 v see figure 50 p_8.4.2 input voltage hysteresis v in(hys) ? 250 ? mv 1) see figure 51 1) not subject to production test, specified by design p_8.4.3 low level input current i in(l) 11025 a v in = 0.8 v p_8.4.4 high level input current i in(h) 21025 a v in = 5.5 v see figure 52 p_8.4.5 den pin low level input voltage range v den(l) -0.3 ? 0.8 v ? p_8.4.6 high level input voltage range v den(h) 2?6v? p_8.4.7 input voltage hysteresis v den(hys) ? 250 ? mv 1) p_8.4.8 low level input current i den(l) 11025 a v den = 0.8 v p_8.4.9 high level input current i den(h) 21025 a v den = 5.5 v p_8.4.10 dsel pin low level input voltage range v dsel(l) -0.3 ? 0.8 v ? p_8.4.11 high level input voltage range v dsel(h) 2?6v? p_8.4.12 input voltage hysteresis v dsel(hys) ? 250 ? mv 1) p_8.4.13 low level input current i dsel(l) 11025 a v dsel = 0.8 v p_8.4.14 high level input current i dsel(h) 21025 a v dsel = 5.5 v p_8.4.15
data sheet 39 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA characterization results 9 characterizati on results the characterization have been performed on 3 lots, wit h 3 devices each. characteri zation have been performed at 8 v, 13.5 v and 18 v, from -40c to 160c. when no dependency to voltage is seen, only one curve (13,5v) is sketched. 9.1 general product characteristics 9.1.1 minimum functi onal supply voltage p_4.2.3 figure 29 minimum functional supply voltage v s(op)_min = f ( t j ) 9.1.2 undervoltage shutdown p_4.2.4 figure 30 undervoltage threshold v s(uv) = f ( t j ) 3,8 4,2 4,6 5 -40 0 40 80 120 160 junction temp (c) vs(op)_min (v) minimum functional supply.vsd undervoltage_shutdown.vsd 3 3,25 3,5 3,75 4 -40 0 40 80 120 160 junction temp (c) vs(uv) (v )
BTS5090-2EKA characterization results data sheet 40 rev. 2.0, 2010-08-02 profet?+ 12v 9.1.3 current consumpt ion one channel active p_4.2.5 figure 31 current consumption for whole d evice with load. one channel active i gnd_1 = f ( t j ; v s ) 9.1.4 current consumptio n two channels active p_4.2.6 figure 32 current consumption for whole d evice with load. two channels active i gnd_2 = f ( t j ; v s ) 9.1.5 standby current for whole device with load p_4.2.7, p_4.2.10 figure 33 standby current for whole device with load. i s(off) = f ( t j ; v s ) current consumption one channel active.vsd 0 3 6 -40 0 40 80 120 160 junction temp (c) i_gnd1 (ma ) i_gnd1 @ 8v i_gnd1 @ 13.5v i_gnd1 @ 18v current consumption two channel active.vsd 0 3 6 9 -40 0 40 80 120 160 junction temp (c) i_gnd2 (ma ) i_gnd2 @ 8v i_gnd2 @ 13.5v i_gnd2 @ 18v 0 2 4 6 -40 0 40 80 120 160 junction temp (c) is(off) (a ) is(off) @ 18v is(off) @ 13.5v is(off) @ 8v
data sheet 41 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA characterization results 9.2 power stage 9.2.1 output voltage drop li mitation at low load current p_5.5.4 figure 34 output voltage drop limitation at low load current v ds(nl) = f ( t j ; v s ) ; i l = i l(0) = 50ma 9.2.2 drain to source clamp voltage p_5.5.5 figure 35 drain to source clamp voltage v ds(az) = f ( t j ) 7 9 11 13 -40 0 40 80 120 160 junction temp (c) vds(nl) (mv ) output voltage drop limitation at low load current.vsd 40 44 48 52 -40 0 40 80 120 160 junction temp (c) vds(az) (v ) drain to source clamp voltage.vsd
BTS5090-2EKA characterization results data sheet 42 rev. 2.0, 2010-08-02 profet?+ 12v 9.2.3 slew rate at turn on p_5.5.11 figure 36 slew rate at turn on d v /d t on = f ( t j ; v s ), r l = 6 9.2.4 slew rate at turn off p_5.5.12 figure 37 slew rate at turn off - d v /d t off = f ( t j ; v s ), r l = 6 9.2.5 turn on p_5.5.14 figure 38 turn on t on = f ( t j ; v s ), r l = 6 dv_dt_on.vsd 0,1 0,3 0,5 -40 0 40 80 120 160 junction temp (c) dv/dt_on (v/s ) dv/dt_on @ 8v dv/dt_on @ 13.5v dv/dt_on @ 18v dv_dt_off.vsd 0,1 0,3 0,5 -40 0 40 80 120 160 junction temp (c) dv/dt_off (v/s ) dv/dt_off @ 8v dv/dt_off @ 13.5v dv/dt_off @ 18v 30 130 230 -40 0 40 80 120 160 junction temp (c) t_on 90% (s) ton 90%@18v ton 90%@13,5v ton 90%@8v ton_90.vsd
data sheet 43 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA characterization results 9.2.6 turn off p_5.5.11 figure 39 turn off t off = f ( t j ; v s ), r l = 6 9.2.7 turn on / off matching p_5.5.16 figure 40 turn on / off matching t sw = f ( t j ; v s ), r l = 6 30 130 230 -40 0 40 80 120 160 junction temp (c) t_off 10% (s) toff 10%@18v toff 10%@13,5v toff 10%@8v toff_90.vsd delta_t_sw_off_on.vsd -50 -25 0 25 50 -40 0 40 80 120 160 junction temp (c) delta t sw (s) delta_t_sw @ 8v delta_t_sw @ 13.5v delta_t_sw @ 18v
BTS5090-2EKA characterization results data sheet 44 rev. 2.0, 2010-08-02 profet?+ 12v 9.2.8 switch on energy p_5.5.19 figure 41 switch on energy e on = f ( t j ; v s ), r l = 6 9.2.9 switch off energy p_5.5.20 figure 42 switch off energy e off = f ( t j ; v s ), r l = 6 0 250 500 750 1000 -40 0 40 80 120 160 junction temp (c) e_on (j) switch on energy @ 18v switch on energy @ 13,5v switch on energy @ 8v 0 250 500 750 1000 -40 0 40 80 120 160 junction temp (c) e_on (j) switch on energy @ 18v switch on energy @ 13,5v switch on energy @ 8v
data sheet 45 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA characterization results 9.3 protection functions 9.3.1 overload condition in the low voltage area p_6.6.4 figure 43 overload condition in the low voltage area i l5(sc) = f ( t j ; v s ) 9.3.2 overload condition in the high voltage area p_6.6.7 figure 44 overload condition in the high voltage area i l28(sc) = f ( t j ; v s ) 20 25 30 35 40 -40 0 40 80 120 160 junction temp (c) il5(sc) (v) il(sc)_5v @ 8v il(sc)_5v @ 13.5v il(sc)_5v @ 18v 10 15 20 -40 0 40 80 120 160 junction temp (c) il28(sc) (v)
BTS5090-2EKA characterization results data sheet 46 rev. 2.0, 2010-08-02 profet?+ 12v 9.4 diagnostic mechanism 9.4.1 current sense at no load figure 45 current sense at no load i is = f ( t j ; v s ), i l = 0 9.4.2 open load detection threshold in on state p_7.5.2 figure 46 open load detection on state hysteresis i l(ol) = f ( t j ; v s ) 0 0,5 1 1,5 2 2,5 -40 0 40 80 120 160 junction temp (c) i_is @ il = 0ma (a ) current_sense_0ma.vsd
data sheet 47 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA characterization results 9.4.3 sense signal maximum voltage p_7.5.3 figure 47 sense signal maximum voltage v s - v is(range) = f ( t j ; v s ) 9.4.4 sense signal maximum current p_7.5.7 figure 48 sense signal maximum current in fault condition i is(fault) = f ( t j ; v s ) 1 2 3 -40 0 40 80 120 160 junction temp (c) v s - v is _range (v) vis_range @ 8v vis_range @ 13.5v vis_range @ 18v iis_fault.vsd 6 16 26 36 -40 0 40 80 120 160 junction temp (c) iis_fault (ma ) iis_fault @ 8v iis_fault @ 13.5v iis_fault @ 18v
BTS5090-2EKA characterization results data sheet 48 rev. 2.0, 2010-08-02 profet?+ 12v 9.5 input pins 9.5.1 input voltage thr eshold on to off p_8.4.1 figure 49 input voltage threshold v in(l) = f ( t j ; v s ) 9.5.2 input voltage threshold off to on p_8.4.2 figure 50 input voltage threshold v in(h) = f ( t j ; v s ) input_pin_low_voltage.vsd 0 0,5 1 1,5 2 -40 0 40 80 120 160 junction temp (c) v_inh(l) (v) i_in(l) @ 8v i_in(l) @ 13.5v i_in(l) @ 18v input_pin_high_voltage.vsd 0 0,5 1 1,5 2 -40 0 40 80 120 160 junction temp (c) v_inh(h) (v)
data sheet 49 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA characterization results 9.5.3 input voltage hysteresis p_8.4.3 figure 51 input voltage hysteresis v in(hys) = f ( t j ; v s ) 9.5.4 input current high level p_8.4.5 figure 52 input current high level i in(h) = f ( t j ; v s ) 0 100 200 300 400 -40 0 40 80 120 160 junction temp (c) v_in(hys) (mv ) v_in(hys) @ 8v v_in(hys) 13.5v v_in(hys) @ 18v input_pin_voltage_hysteresis.vsd 0 5 10 15 20 25 -40 0 40 80 120 160 junction temp (c) i_inh(h) (a) input_pin_high_current.vsd
BTS5090-2EKA application information data sheet 50 rev. 2.0, 2010-08-02 profet?+ 12v 10 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. figure 53 application diagram with BTS5090-2EKA note: this is a very simplified example of an application ci rcuit. the function must be verified in the real application. table 11 bill of material reference value purpose r in 4.7 k protection of the micro controller du ring overvoltage, reverse polarity guarantee bts5090- 2eka channels off during loss of ground r den 4.7 k protection of the micro controller du ring overvoltage, reverse polarity guarantee bts5090- 2eka channels off during loss of ground r pd 47 k polarization of the output improve BTS5090-2EKA immunity to electromagnetic noise r dsel 4.7 k protection of the micro controller du ring overvoltage, reverse polarity guarantee bts5090- 2eka channels off during loss of ground r is 1.2 k sense resistor out out out out a/d vss vdd micro controller in0 in1 den dsel is gnd out0 out1 v s v bat c sense application example.svg z1 r/l cable r/l cable r/l cable c out1 c out0 r in r in r den r dsel r a/d r sense r is r gnd v dd r pd r pd c vs r ol t 1 d z2
data sheet 51 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA application information 10.1 further application information ? please contact us to get the pin fmea ? existing app. notes ? for further information you may visit http://www.infineon.com/profet r sense 4.7 k overvoltage, reverse polarity, loss of ground. value to be tuned with micro controller specification. r ol 1.5 k ensure polarization of the BTS5090-2EKA output during open load in off diagnostic r a/d 4.7 k protection of the micro controller du ring overvoltage, reverse polarity d bas21 protection of the bts509 0-2eka during reverse polarity r gnd 1 k to keep the device gnd at a stable potential during clamping z1 7 v zener diode protection of the micro controller during overvoltage z 2 36 v zener diode protection of the devi ce during overvoltage t1 bc 807 switch the battery voltage for open load in off diagnostic c sense 100 pf sense signal filtering c vs 100 nf filtering of the voltage spikes on the battery line c out0 4.7 nf protection of the bts5 090-2eka during esd and bci c out1 4.7 nf protection of the bts5 090-2eka during esd and bci table 11 bill of material (cont?d) reference value purpose
BTS5090-2EKA package outlines data sheet 52 rev. 2.0, 2010-08-02 profet?+ 12v 11 package outlines figure 54 pg-dso-14-40 ep (plastic dual small outlin e package) (rohs-compliant) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. gree n products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps01207 0.2 -0.1 8? max. 0?...8? 1.27 0.41 ?.09 2) a-b 0.2 m c 14x d seating plane (1.47) 1.7 max. stand off c c 0.08 -0.1 0.1 +0 8? max. 0?...8? 0.35 x 45? 3.9 ?.1 1) 0.1 d c2x ?.25 0.64 6 d d ?.2 0.2 m +0.06 0.19 8? max. a 17 8 14 b c 0.1 a-b 2x ?.1 8.65 index marking 6.4 bottom view ?.1 ?.1 2.65 7 1 14 8 2) does not include dambar protrusion of 0.13 max. 1) does not include plastic or metal protrusion of 0.15 max. per side 3) jedec reference ms-012 variation bb
data sheet 53 rev. 2.0, 2010-08-02 profet?+ 12v BTS5090-2EKA revision history 12 revision history version date parameter changes 2.0 2010-05-31 creation of the data sheet
edition 2010-08-02 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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